When wiring in semiconductor devices is reduced to a microscopic size so as to highly integrate the semiconductor devices, and when current density of the wiring is increased so as to improve operation speed of the semiconductor devices, a problem of the wiring becoming less reliable due to electromigration occurs.
Al wiring, which is widely used in the current semiconductor devices, has a low electromigration resistance. Therefore, various materials for wiring to replace the Al wiring have been examined. Cu is attracting attention as one of the materials for wiring to replace Al.
Methods of forming Cu wiring includes a method of forming a photoresist as a resist on a Cu thin film that is formed on a substrate, patterning the resist by the photolithography, and etching the thin film by isotropic wet etching.
This method, however, causes a problem of reducing the width or height in part of the wiring as shown in FIG. 2(a), resulting in a disconnection of the wiring or an increase of resistance.
This problem arises because a surface of the Cu thin film tends to have a surface reaction such as oxidation at a relatively low temperature, which makes the surface condition thereof not stable. Depending on the surface condition of the Cu thin film, adhesion between the Cu thin film and the photoresist may be significantly decreased.
If the adhesion between the photoresist and the surface of the Cu thin film is weak, when forming the photoresist on the Cu thin film and patterning the photoresist, part of the resist comes off. Consequently, the above problem arises.
As described above, if the resist is not adhered firmly to the surface of the Cu thin film, the wiring cannot be formed to the design dimensions (the width and the height of the wiring).
Patent Document 1 discloses a technique of etching Cu in a shape of wiring by the RIE (Reactive Ion Etching) method, which is anisotropic etching.
In this technique of forming the Cu wiring, as shown in FIG. 9(a), a TiN barrier layer 112 (lower barrier layer), a Cu layer 114, and a TiN barrier layer 116 (upper barrier layer) are deposited in this order on a base 110. Thereafter, an SiO2 etching mask 118a is formed on the TiN barrier layer 116, which is the upper barrier layer.
Next, by the RIE method, the upper TiN barrier layer 116, the Cu layer 114, and the lower TiN barrier layer 112 are etched in this order in the shape of the wiring over the etching mask.
Here, a mixed gas containing SiCl4, Cl2, and N2, for example, is used as an etching gas. As the upper TiN barrier layer 116, the Cu layer 114, and the lower TiN barrier layer 112 are etched as shown in FIG. 9(b) by controlling the atomic ratio of Si to Cl in the etching gas, an SiOxNy barrier layer as a sidewall barrier layer 122 is deposited on sidewalls of the etched layers.
As described above, in the technique of forming the Cu wiring disclosed in Patent Document 1, when the Cu layer is etched, reaction products are formed from the etching mask and the reactive etching gas. The reaction products are deposited on side surfaces 1141 where the Cu layer is etched, forming the sidewall barrier layer 122.
Therefore, the sidewall barrier layer 122 can be formed while etching the layers, thereby eliminating a heat treatment for forming the sidewall barrier layer 122. Consequently, the sidewall barrier layer 122 can be formed at such a low temperature that semiconductor elements are not degraded.